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yyyyyy x. yyyyyy 0000 xxxxxx xxxx , xxxx , xxxxx 00000
xxx-xxx-xxxx
abc@xyz.com
objective
performance-driven it professional specializing in software programming, quality assurance, testing and engineering eager to contribute technical proficiencies as well as dynamic project management skills toward supporting operations of a progressive organization in a software design project lead role.
career profile
ø master of science degree in computer science and over 18 years of intensive experience.
ø skilled consultant and advisor to clients and senior management.
ø holder of numerous u.s. patents and author of many scientific papers.
ø knowledgeable in algorithms, simulation, ip/asic design, optimization/synthesis and placement/global routing systems.
ø proven testing and troubleshooting capacity.
ø well-versed in full life cycle project management.
ø award-winning record of progression to positions of increasing authority and responsibility.
ø proficient in multiple, advanced applications (see below).
ø adept in installation, set-up and management software upgrades.
ø effectively interact with diverse groups and professionals at all levels.
ø well-organized multi-tasker with strong detail orientation.
ø adept in aligning it contributions with organizational objectives.
ø enthusiastic team leader/player.
technology skills
c, c++, java, perl, shell, sql, html, jdbc, servlet, asic component design
professional experience
plato/cadence design systems 2002 - present
project lead
originated and facilitate dfm wire-spreading routing to improve signal integrity and timing, cluster & trunk routing and partitioning of hierarchical and multi-thread global routing.
upgrade global-route qor (quality of result) with self-adaptive, auto-adjusting cost-function curves, congestion & wire-length weights and diffusion costs, including automatic rollback.
develop web-based infrastructure for automatic local nightly build, regression test log data parsing & extraction, qor monitoring & alarming and auto-release promotion & archiving.
initiated r&d qa, check-in, code branching and release procedures & policies.
cadence achievement award, 2008.
chameleon systems, inc. 2001 - 2002
project lead
developed and constructed award-winning cad package to generate control circuits and automatic selection of architecture based on cost.
designed timing/congestion-driven placement and routing tool for reconfigurable company platform, including manual gui editor, drc checking and qor analysis.
recipient of outstanding effort award, 2001.
perfect.com 2000 - 2001
senior software engineer
designed advanced heuristic system for non-linear programming optimization algorithms, java applications and database performance analysis and improvement.
designed server-side java applications such as net market maker, exchanger and account manager.
yyyyyy x. yyyyyy
page two
earlier experience
prior to 2000, employed by synopsys, inc. in capacity of project lead for designware foundation improving product qor, boosting company revenue, reviewing and verifying qor policies, promoting new products, inventing new optimization algorithms and developing designware components; silicon valley research, inc. as project lead and senior technologist inventing new physical layout algorithms, implementing floorplanner and compactor for block/standard-cell mixed designs, improving placer speed performance and enhancing gate-array functionality (president s club awards) and sed systems, inc. as senior software engineer embedding software, converting land to satellite telecommunications protocols and stationing call management.
education
university of saskatchewan, city, saskatchewan, canada
master of science, computer science
tsinghua university, beijing, china
master of engineering, electrical engineering
bachelor of science, computer science
patents and publications
ø d. noice, p. liu, p. huang, j. li, j. zhu, yield analysis and improvement in encounter, proceeeding of ctc, 2005
ø j. zhu, fast parallel multiplier implemented with improved tree reduction schemes, u.s. patent #6490608, december 2002, synopsys, inc.
ø t. ding and j. zhu, integrated circuit layout, u.s. patent #5 xxx-xxx-xxxx , svr, inc.
ø j. zhu, m. abd el-barr and c. mccrosky, á new theory for testability-preserving optimization of combinational circuits, vlsi design, 1996, vol. 5, no.1, pp.59-75.
ø j. zhu, m. abd el-barr, on the optimization of mos circuits, ieee transaction on circuits and systems, vol.40, no.6, june 1993, pp. 412-422.
ø j. zhu, m. abd el-barr, tsc-3: a totally self-checking checker and corrector with self-exercising, international electronics journal, vol.74, no.5, may 1993, pp. 683-695.
ø c. mccrosky, m. abd el-barr, j. roe, h el-gebaly, w. li, m. mahroos, y. xu, j. zhu, synthesis of vlsi circuits from parallel distributed behavioral specifications, proceeding of canadian conference on vlsi 1993, pp. 6b1-6b6
ø j. zhu, y. chen, an improved bandwidth minimization bbl placement algorithm, proceeding of ee international conference on circuits and systems 1989, pp. 167-170.
ø j. zhu, r. kelly, improve system throughput using designware duplex components, synopsys technical forum for design automation information, q1, 2000.
ø j. zhu, connecting different bit-width subsystems using foundation asymmetric i/o fifo family, synopsys technical forum for design automation information, 1999.
ø j. zhu, designware foundation supports ieee numeric standard package, synopsys technical forum for design automation information, 1999.
ø j. zhu, r. kelly, architectural diversity - the key to design compiler optimization, synopsys technical forum for design automation information, q2, 1998.
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