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Yyyyyy x. yyyyyy

0000 xxxxxx xxxx , xxxx , xxxxx 00000

Phone: (xxx-xxx-xxxx

abc@xyz.com

 

Creative and industrious Hardware Design Engineer seeking opportunity where extensive talents will provide an immediate and positive impact to a dynamic and progressive organization.

 

Qualifications Profile

 

         Offer 15+ years of electrical engineering experience with considerable strengths in design verification of high-frequency mixed-signal communication channels.

         Proficiency in operating broad spectrum of lab test equipment such as scopes, analyzers and signal generators.

         Able to plan, develop and execute procedures, processes, and methodologies to optimize product performance, quality, manufacturability, durability, and reliability. 

         Advanced skills throughout product/system development process including concept creation, schematic capture, PCB layout design verification, testing and debugging.

         Collaborative, versatile and committed to results; equally strong as a project leader or team member, and quickly adapt to new technologies.

         Adept with embedded systems architecture such as ARM-based SOC in hard disk drives.

         Highly developed troubleshooting, research, and multi-tasking skills.

         Proven talents with protocols such as audio, video, firewire, USB, Ethernet and DDR2.

         Familiar with digital design in FPGA and verilog.

         Able to design and develop magnetic r/w sensors and capacitive proximity sensors.

 

Professional Experience

 

LSI Corp., Milpitas , CA, 2008 to Present

Principal Design Validation Engineer

  • Analyze and fine-tune high-frequency mixed-signal embedded system SOC used in hard disk drives and designed with 40nm CMOS technology.
  • Perform hardware functional verification, signal characterization, and swift resolution of cross-functional issues relating to architecture such as performance, power consumption and thermal behavior.
  • Troubleshoot and rectify production issues relating to design margins and quality, conduct in-depth failure analysis, and meticulously ocument findings.
  • Exhibit proficiency with blocks such as serial and parallel interface, high speed NRZ data bus and LDPC detector/decoder.

 

Marvell Semiconductors, Santa Clara, CA, 2000 to 2008

Lead Design Verification & Application Engineer         (2003 to 2008)

  • Applied sharp attention to detail in preparing design specifications for 2 to 3 GHz line driver/wideband  RF  LNA/device including functional blocks such as prefiltering, amplification, high speed line driver, ADC, DAC and biasing of external magnetic sensors.
  • Participated in chip technology evaluation and selection and architecture design.
  • Resourcefully designed bench silicon evaluation platform consisting of test PCB, host interface and test software using OrCAD schematic capture, PSPICE simulation and PADs layout.
  • Effectively integrated ALTERA fpga and PC interfaces such as USB and parallel port as well as custom transmission lines.

 

Continued ►

 

 

Yyyyyy x. yyyyyy ~ Page 2 of 2

 

Professional Experience continued

 

Sr. SERDES Application Engineer C SATA/SAS devices       (2002 to 2003)

  • Performed SATA physical layer characterization, conducted thorough compliance testing, and provided critical design support for silicon validation.
  • Facilitated signal integrity simulations using HSPICE, Agilent ADS and Tek IConnect simulators and completed s-parameter measurements via Agilent E5071B Network Analyzer.

  

Sr. Validation Engineer C HDD PRML Read  Channel     (2000 to 2002)

  • Engineered high-speed mixed-signal communication IC used for hard disk drive data recoding and reproduction.
  • Spearheaded bench-level silicon verification and characterization of analog and digital functional blocks such aVGA, Continuous-Time Filter, ADC (analog to digital convertor) and FIR (finite impulse response).
  • Proactively attended design reviews and contributed to design of silicon evaluation test PCB.
  • Diligently prepared data sheet and application notes.

 

Quantum Corporation, Milpitas, CA, 1993 to 2000

Sr. Read/Write Engineer, PRML channel C 3.5 inch Drives          (1995 to 2000)

  • Critically evaluated PRML channel and preamp ICs at bench and drive level.
  • Exercised extensive capabilities in schematic design to achieve board-level integration of RDC and flex-level for preamp.
  • Devised BPI/TPI (bits per inch/tracks per inch) track formats, channel training and error recovery algorithms.
  • Adeptly conducted and documented BER (bit error rate) testing and evaluation of head/media.

 

Sr. Heads/Media Development Engineer C GMR Heads and Preamps          (1993 to 1995)

  • Demonstrated strong project management, organizational and technical expertise to decisively develop head/media design specification for target recording densities.
  • Analyzed latest head/media and preamp components on Guzik spin stand tester.
  • Explored effect of preamplifier parameters on read and write processes.

 

Prior Background:

Advanced Recording Technology Engineer, Maxtor Corporation, San Jose, CA

Equipment Design Engineer, StorageTek - Media Division, San Jose, CA

 

Education

 

BS Degree in Electrical Engineering, University of Texas, Austin

 

Professional Development:

 

     Magnetic Recording                            High-speed PCB Design

     CMOS Analog Design                         Wireless Design & Measurement

     Embedded System Design                              C/C++ Programming

 

Member of IEEE

 

Patents

 

Circuits, Systems and Methods for Capacitive Fly Height Measurement                     US Patent 7,256,957 

Circuits, Systems and Methods for Capacitive Proximity Detection                           US Patent 7,623,315

Circuits, Systems and Methods for Generating Bias Power                                  US Appl No. 11/355,459

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