Yyyyyy x. yyyyyy

0000 xxxxxx xxxx , xxxx , xxxxx 00000

Phone: (xxx-xxx-xxxx

abc@xyz.com

 

 

Profile

 

  13 years of electrical engineering experience and over 10 tapeouts; exceptional abilities with  high speed circuit and physical design, low-power memory, register files and CAM design, datapath design, and standard cell, gate array and datapath library design, layout and characterization.

  Adept at designing complex electronic systems using state-of-the-art methodologies and fabrication processes.

  Proficiency with CMOS technology and using EDA (electronic design automation) tools.

  Design high-speed low power custom and semi-custom ICs including sub-2Ghz and multiple core microprocessors via cutting-edge technologies.  

  Able to coordinate and oversee precise floor-planning and layout supervision of functional blocks and chip integration involving single- and multiple-core processors.

  Effective at static timing analysis and timing simulation, quality process and documentation, flow automation, and power/clock distribution.

  Highly skilled throughout the complete product development life cycle.

 

Professional Experience

 

Sun Microsystems, Santa Clara, CA, 2002 to Present

Staff Circuit Design Engineer C Arithmetic Circuit Design and Register Files Design

         Create circuit and physical designs for custom and semi-custom high-speed low power blocks.

         Perform arithmetic circuit design via simulation, analysis and design of high-speed adders and shifters in target processes.

         Design low power register files consisting of RAM and CAM blocks with multiple write/read/compare ports in deep sub-micron technologies (65nm and 45nm).

         Facilitate Spice simulations to analyze and validate functionality, performance, power and area, strategically modifying designs to ensure seamless operation over PVT (process, voltage and temperature) corners.

         Obtain and manipulate data to create timing models used in full-chip timing.

         Document and present findings in formal reviews.

 

Cradle Technologies, Fremont, CA, 2000 to 2002

Circuit Design Engineer Manager C Circuits and Libraries

         Directed team of circuit and physical design engineers in supporting broad-based customer needs.  

 

Continued ►

 

 

 

 

 

Jessie Son Le ~ Page 2 of 2

 

Professional Experience continued

 

         Spearheaded complete design and development of new sample library of portable standard cells.

         Supervised and contributed to circuit and physical design methodology development with an emphasis in datapath implementation and integration.

         Established datapaths and buffer designs in custom and P&R (place and route) layouts while executing clock buffer tuning and datapath sizing to optimize timing analysis.

         Executed in-depth backend flow checks encompassing noise analysis, signal integrity, functional verification, ATPG, static circuit checks, slow node fixes, IR drop and EM analysis.

 

Quantum Effect Devices (QED), Santa Clara, CA, 1996 to 2000

Circuit Design Engineer C Circuit, Physical Design and Integration of Microprocessors

         Directed team in circuit and physical design of 1.8Ghz 90nm CPU (E11K) core and peripherals and achieve seamless integration with 3^rd party IP into a SOC.

         Ported multi-port register file design from 0.18u to 0.13u process technology inclusive of Spice simulations, leakage control, re-layout, timing analysis and modeling, circuit checks, and reviews. 

         Functioned as Lead Circuit Designer for company s first 0.18u processor-based SOC (Alpine).

         Redesigned sub-blocks of IU and MMU requiring strong skills in critical path simulations, formal verification, timing analysis, layout supervision, and pre- and post-layout circuit simulations.

         Oversaw circuit and physical design of highly successful TLB of RM7000 microprocessor in 0.25u, compatible between process generations and reducing area and cost while strengthening overall performance.

         Managed design of p-level shifter and fast equality comparator from circuit design, layout and integration, to in-depth timing analysis and modeling.

         Assisted Physical CAD Engineer in coordinating datapath placement and integration tool, substantially accelerating layout time of datapath blocks without affecting performance.

 

Prior background includes role as Engineer Intern, Research & Development Group C Conner Peripherals, San Jose, CA 1995 to 1996.

 

Education

 

MS in Electrical Engineering, Stanford University, Palo Alto, CA, 2005

BS in Electrical Engineering and Computer Science (EECS), U.C. Berkeley, Berkeley, CA

 

Additional Training:

 

Computer Architecture; Semiconductor Processes; Circuit Design,

Stanford Center for Professional Development

 

EDA Tools: Cadence and Synopsys