Solutions-focused RF Test and System Engineer eager to contribute technical proficiencies as well as dynamic project management skills toward supporting the employer in optimizing results.
VLSI System Design
Operating System Design
Gate Array Design
FPGA Pattern Generation
VLSI Tool (Opus)
PLL Jitter Measurement
Ø Strong technical background within the automotive industry with extensive knowledge of various systems, including: Project Lifecycle Management, Team Training and Mentoring, Engineering Change Management, AGILE Process Methodology, Risk Assessment and Management, and Hardware Integration and Testing.
Ø Proficient at guiding multiple business partnership teams in collaborative projects over the production lifecycle.
Ø Ability to work independently on multiple engineering projects simultaneously and efficiently.
Ø Effectively lead top-performing teams.
Ø Possess an extensive knowledge of engineering practices, policies, and regulations and can apply this knowledge in terms of production efficiency, forecasting and projections, as well as feasibility analyses.
Ø Conducts numerous phases of product launches including technical development, scheduling, addressing and resolving technical challenges, and negotiation of cost.
Ø Possess in-depth knowledge of market deployments, cross-functional team leadership, as well as Vendor Relations Management.
Ø Multiple years of experience as an Engineer in numerous applications and settings with the ability to make an immediate impact on operations and revenue.
Ø Excel in defining and implementing policies, procedures and operational systems that boost productivity, efficiency and quality of operations.
Ø Competent leader and mentor who is able to create a team environment, including building collaborative relationships, training peers to perform at maximum efficiency, and the capacity to form cross-functional coalitions in order to ensure knowledge is shared across departmental lines.
Ø Consistently focus on ensuring development of efficiency best-practices.
Ø Proven ability to adapt strong safety and technical skills to diverse organization needs.
Ø Contribute working knowledge of ISO 9001 standards compliance toward proficiently developing supporting documentation.
Senior Product Development Engineer, MathStar Inc. 2007-2008
Performed fault isolation, troubleshooting, and testing packaged silicon to measure the amount of Static leakage and to isolate FPOA Functional failures, and then created a test flow for Agilent 93000.
Designed, created, and tested script programs using Python to automate Agilent oscilloscope 80604B, Temperature control unit FTC100, and Melcor Chiller for Validation/Characterization. Features include: RS232 and Ethernet host interface.
Performed Pre Silicon Verification and functional testing of FPOA object blocks using Model-sim.
Pre Silicon Verification and functional testing of FPOA object arrays, using Verilog, Perl, and C/C++ to Validate LBIST signatures of the FPOA arrays.
Designed and developed Test plan and Test flow specifications for validation and characterization and set standards for functionality and reliability of new FPOA products. The Test Plan and Test flow includes JTAG, SICC, I/O Parametric, Array LBIST, PCIe X8 PHY, IRAM MBIST, PLL/DLL, and DDR2 PHY tests.
Consulted with Design and Software Engineers to insure device testability and development of a test/characterization plan.
Responsible for summarizing all product yield and performance data in a characterization report and reviewing the data with all internal customers.
Worked closely with offsite product and test engineers to ensure smooth migration of new FPOA product to production.
Assisted manufacturing and reliability groups as required to meet product test requirements for coverage, test cost and yield.
Validated test content of Agilent test programs, and assisted in test failure debug.
Analyzed wafer sort (for good die) and class raw data and produced technical reports.
Senior Product Development Engineer, Lattice Semi-Conductor Corp. 1996-2007
Validated and characterized GALs, CPLD, and FPGA products on time and under budget, from design phase till the release of products to manufacturing.
Created, Developed and debugged test programs for GALs, CPLDs, and FPGAs products for commercial, industrial, and military applications, utilizing Q2/620, Impact, Credence LT 1101, Teradyne 750 and Agilent 93000 testers.
Performed failure analysis on Customer returns, using a test program, a Curve tracer, and a programmable platform.
Resolved a problem with (Q2/520) interface loadboard, which resulted in 10% wafer sort good die yield improvement across all product families.
Designed test patterns and performed test simulation on FPGA products, using C/C++, Perl, Verilog RTL, and Test Bench.
Designed/Simulated counters, using Schematic and Waveform editors, Verilog HDL, EPIC, Timing Analysis, Timing Report, Preference Editor, Lattice FPGA Floor planner, Power Calculator, Synthesis, and Model-sim.
Performed fault isolation, troubleshooting, and testing new silicon wafers using Teradyne 750, Agilent 93000, Microprotech REL 4800, Parameter analyzer 4145A, and EMMI.
Performed Pre Silicon Verification and functions testing of PFGA object blocks using Model-sim.
Pre Silicon Verification and functional testing of FPGA object arrays, using Verilog, and Perl, to Validate FPGA arrays.
Performed complex PLL Jitter analysis utilizing Wavecrest 3000, wavecrest DTS 550, oscilloscope HP602, signal generator HFS 9003, voltmeters, and Voltage sources.
Organized PowerPoint presentations and held monthly ispLEVER FPGA training courses for all engineers.
Prepared Pre Silicon detailed documentation for ordering silicon wafers, assembled parts, test hardware and microproping equipment.
Responsible for design and development of probe cards and bench loadboards for speed and noise measurements.
Analyzed and wrote Manufacturing documentation and set standards for functionality and reliability of FPGA products.
Analyzed wafer sort (for good die) and class raw data and produced customer characterization reports, using SAS software.
Validated and Qualified Lattice Semi-conductor CPLD and FPGA products for Automotive AEC-Q100.
Worked with various offshore assembly and test facilities to insure product release schedules are met.
Test Engineer, Micron Technology 1996
Created, developed and debugged test programs for memory devices such as 64K, 256K, 1MEG, 4MEG, and 16MEG DRAMS, VRAMS and SRAMS, on an ATE, such as Mega Test (Q2/520), Genesis II, and Teradyne 994/997.
Designed test patterns, test flows, timing and summaries to meet new product specifications, using C/C++.
Designed interface software for DAYMARC 3287, SYMTEK MP408, and ADVANTEST M3741A.
Retrieve and analyze data from VAX and Ethernet networks pertaining to major problems with products or test systems.
Consult with QA and product engineering to find the best solutions to any major failure or new specs.
n M.S. C VLSI Design, University of Portland
- Projects: Developed 8-bit Pipeline Multiplier NMOS chip using VLSI CAD tools including; mask layout editors, design-rules and electrical-rule checkers, circuit extractor, timing verifier, and simulators. Multiplier was used later in an FFT.
n B.S. C Electrical Engineering / Minor: Computer Architecture, University of Portland
- Projects: Designed Schmitt Triggers, Decoders, and Sense Amplifiers. Hand Analysis and Computer simulation (Using SPICE) were used to compute voltages, currents, noise margins, internal capacitance's, propagation delay and power consumption.
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